(1) Technical Field
This invention relates generally to packaging systems for semiconductor integrated circuits, and more particularly, to a novel, reusable, antistatic strapping method for securing stacks of trays containing arrays of semiconductor devices during testing operations, and which also allows for writing lot identification information directly onto the straps.
(2) Description of the Prior Art
In view of the trend for higher and higher packing densities for semiconductor integrated circuits or chips, electronic manufacturers have developed, in recent years, extremely miniaturized rectangular-shaped parts of the type having no terminal leads, such as pin grid array packages. Some of these types of pin grid array package structures are formed with solder balls on their bottom surface rather than with external terminal pins and are referred to as "ball grid arrays" (BGA) packages. Over the years, BGA packages of this type have become even smaller with extraordinary small outer dimensions and are somethimes referred to as "micro ball grid arrays," or micro BGA packages. For example, a typical micro BGA package having forty-four solder balls on its bottom surface may have a length dimension of about 11 mm, a width dimension of about 6 mm and a thickness of about 2 mm.
During the manufacturing of semiconductor device packages, these packages are stored and transported to and from various types of processes or manufacturing equipment for carrying out different manufacturing or assembling steps. For example, the semiconductor device packages may be assembled, marked, tested, inspected and the like during which time the packages are handled and transported between the various manufacturing processes and/or machines. Further, after the processing steps have been completed, the semiconductor device packages are also packed and transported from a chip manufacturer's site to an assembly station at a customer's site where further assembly or testing operations are performed.
Heretofore, there is known in the prior art of a chip carrier tray having a plurality of separate compartments or pockets for accommodating a number of individual semiconductor device packages spaced apart from each other. Such a prior art chip carrier tray with a cover is illustrated in FIG. 1 The chip carrier tray 11 and the cover 12 are both formed of a general square-shaped configuration. FIG. 2 shows a cross-sectional view of the tray 11 which includes a plurality of separate compartments 15 each being capable of holding therein a single semiconductor device package 10.
Conventionally, chip carrier trays are transported between manufacuring sites and processes in stacks of up to (and about) ten trays. The trays are banded together using antistatic strapping material 13 and are securely sealed by heat activation. The straps 13 must be cut and discarded at each manufacturing or processing stage. The restrapping process requires that many strapping machines be maintained in every corner of the test floor to minimize the transportation distance of unstrapped trays. In addition, the strapping material itself must be replaced at each step, a costly proposition for the manufacturer and/or end user.